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| CY28343 Zero Delay SDR/DDR Clock Buffer Features * Phase-lock loop clock distribution for DDR and SDR SDRAM applications * One-single-end clock input to 6 pairs DDR outputs or 13 SDR outputs. * External feedback pins FBIN_SDR/FBOUT_SDR are used to synchronize the outputs to the clock input for SDR. Table 1. Function Table SELDDR_SDR# 1= DDR Mode CLKIN 2.5V Compatible 3.3V Compatible SDRAM(0:12) OFF DDRT/C(0:5) Active 2.5V Compatible OFF FBIN_DDR 2.5V Compatible OFF FBOUT_DDR Active 2.5V Compatible OFF FBIN_SDR FBOUT_SDR OFF OFF * External feedback pins FBIN_SDR/FBOUT_SDR are used to synchronize the outputs to the clock input for DDR. * SMBus interface enables/disables outputs. * Conforms to JEDEC SDR/DDR specifications * Low jitter, low skew * 48 pin SSOP package 0 = SDRAM Mode Active 3.3V Compatible Active 3.3V Compatible Active 3.3V Compatible Block Diagram Pin Configuration[1] SCLK SDATA Control Logic VDD_2.5V FBOUT_DDR VDD_3.3V DDRT(0:5) DDRC(0:5) CLKIN FBIN_DDR VDD_3.3V FBOUT_SDR PLL *SELDDR_SDR FBIN_SDR SDRAM (0:12) VDD_3.3V SDRAM0 SDRAM1 SDRAM2 SDRAM3 VSS VDD_3.3V SDRAM4 SDRAM5 CLKIN SDRAM6 SDRAM7 VSS VDD_3.3V SDRAM8 SDRAM9 SDRAM10 SDRAM11 VSS VDD_3.3V SDRAM12 FBOUT_SDR FBIN_SDR* VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 SELDDR_SDR#* FBIN_DDR* FBOUT_DDR VDD_2.5V DDRT5 DDRC5 DDRT4 DDRC4 VSS VDD_2.5 DDRT3 DDRC3 DDRT2 DDRC2 VSS VDD_2.5V DDRT1 DDRC1 DDRT0 DDRC0 VSS VDD_3.3V SCLK** SDATA** Note: 1. Pins marked with [*] have internal pull-down resistors. Pins marked with [**] have internal pull-up resistors. Cypress Semiconductor Corporation Document #: 38-07369 Rev. *A * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 Revised December 26, 2002 CY28343 Pin Description[2, 3] Pin 10 47 23 30,32,36,38 42,44 29,31,35,37 41,43 2-5,8,9 15-18,21 46 Name CLKIN FBIN_DDR FBIN_SDR DDRT(0:5) DDRC(0:5) SDRAM(0:12) FBOUT_DDR I/O I I PD I PD O O O O Clock Input. Reference the PLL Feedback Clock Output. Connect to FBOUT_DDR for accessing the PLL. See Function Table on page 1 Feedback Clock Input. Connect to FBOUT_SDR for accessing the PLL. See Function Table on page 1 Clock Outputs. True copies of the CLKIN input Clock Outputs. Complementary copies of the CLKIN input Clock Outputs. True copies of the CLKIN input Feedback Clock Output. Connect to FBIN_DDR for normal operation. A true copy of the CLKIN input. The delay of the PCB trace RC at this output will control Input Reference/DDR Output Clocks phase relationships. Feedback Clock Output. Connect to FBIN_SDR for normal operation. A true copy of the CLKIN input. The delay of the PCB trace RC at this output will control Input Reference/ SDR Output Clocks phase relationships. SDR or DDR Select Pin. See Function Table on page 1 Serial Clock Input. Clocks data at SDATA into the internal register. Serial Data Input. Input data is clocked to the internal register to enable/disable individual outputs. This provides flexibility in power management. 3.3V power supply for SDR outputs and two line serial Interface 2.5V power supply for DDR outputs Common Ground Description 22 FBOUT_SDR O 48 26 25 1,7,14,20,27 33,39,45 SELDDR_SDR# SCLK SDATA VDD_3.3V VDD_2.5V I PD I PU I/O PU 6,13,19,24,28 VSS ,34,40 Notes: 2. PU = internal pull-up PD = internal pull-down. 3. A bypass capacitor (0.1 mF) should be placed as close as possible to each positive power pin (<0.2"). If these bypass capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces. Power Management The individual output enable/disable control of the CY28343 allows the user to implement unique power management schemes into the design. Outputs are in LOW state when disabled through the two-line interface as individual bits are set LOW in Byte0 to Byte2 registers. The feedback output FBOUT_DDR and FBOUT_SDR cannot be disabled via two-line serial bus. Zero Delay Buffer When used as a ZERO delay buffer the CY28343 will likely be in a nested clock tree application. For these applications the CY28343 offers single-end input as a PLL reference. The CY28343 then can lock onto the reference and translate with near zero to low-skew outputs. For normal operation, the external feedback input, FBIN_DDR and FBIN_SDR, are connected to the feedback output, FBOUT_DDR and FBOUT_SDR. By connecting the feedback output to the feedback input the propagation delay through the device is eliminated. The PLL works to align the output edge with the input reference edge thus producing a near zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. Document #: 38-07369 Rev. *A Page 2 of 10 CY28343 Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions such as individual clock output buffers, etc., can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operation from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individual indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). T Table 2. Command Code Definition Bit 7 (6:0) 0 = Block read or block write operation 1 = Byte read or byte write operation Description Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 .... .... .... .... Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 Bit'00000000' stands for block operation Acknowledge from slave Byte Count - 8 bits Acknowledge from slave Data byte 0 - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data Byte N/Slave Acknowledge Data Byte N - 8 bits Acknowledge from slave Stop Description 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 .... .... .... .... Bit Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 Bit'00000000' stands for block operation Acknowledge from slave Repeat start Slave address - 7 bits Read Acknowledge from slave Byte count from slave - 8 bits Acknowledge Data byte from slave -8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data bytes from slave/Acknowledge Data byte N from slave - 8 bits Not Acknowledge Stop Block Read Protocol Description Document #: 38-07369 Rev. *A Page 3 of 10 CY28343 Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write Acknowledge from slave Description 1 2:8 9 10 Bit Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits'1xxxxxxx' stands for byte operationbit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address - 7 bits Read Acknowledge from slave Data byte from slave - 8 bits Not Acknowledge stop Byte Read Protocol Description Command Code - 8 bits'1xxxxxxx' stands for 11:18 byte operationbit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Byte Count - 8 bits Acknowledge from slave stop 19 20 21:27 28 29 30:37 38 39 19 20:27 28 29 Byte 0: Output Register (1 = Enable, 0 = Disable)[4] Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 48 Pin # 29,30 31,32 35,36 37,38 41,42 43,44 Description DDRT/C0. 1 = Enable, 0 = Output disabled asynchronously in a low state DDRT/C1. 1 = Enable, 0 = Output disabled asynchronously in a low state DDRT/C2. 1 = Enable, 0 = Output disabled asynchronously in a low state DDRT/C3. 1 = Enable, 0 = Output disabled asynchronously in a low state DDRT/C4. 1 = Enable, 0 = Output disabled asynchronously in a low state DDRT/C5. 1 = Enable, 0 = Output disabled asynchronously in a low state Reserved SELDDR_DDR hardware setting value. Read only. Byte 1: Output Register (1 = Enable, 0 = Disable)[4] Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Pin # 12 11 9 8 5 4 3 2 Description SDRAM7. 1 = Enable, 0 = Output disabled asynchronously in a low state SDRAM6. 1 = Enable, 0 = Output disabled asynchronously in a low state SDRAM5. 1 = Enable, 0 = Output disabled asynchronously in a low state SDRAM4. 1 = Enable, 0 = Output disabled asynchronously in a low state SDRAM3. 1 = Enable, 0 = Output disabled asynchronously in a low state SDRAM2. 1 = Enable, 0 = Output disabled asynchronously in a low state SDRAM1. 1 = Enable, 0 = Output disabled asynchronously in a low state SDRAM0. 1 = Enable, 0 = Output disabled asynchronously in a low state Note: 4. These bits will be ignored in DDR mode. See Table 1 on page 1. Document #: 38-07369 Rev. *A Page 4 of 10 CY28343 Byte 2: Output Register (1 = Enable, 0 = Disable)[4] Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 21 18 17 16 15 Pin # Reserved for device test. Select drive strength for SDR outputs. 1 = Low drive, 0 = High drive Reserved SDRAM12. 1 = Enable, 0 = Output disabled asynchronously in a low state SDRAM11. 1 = Enable, 0 = Output disabled asynchronously in a low state SDRAM10. 1 = Enable, 0 = Output disabled asynchronously in a low state SDRAM9. 1 = Enable, 0 = Output disabled asynchronously in a low state SDRAM8. 1 = Enable, 0 = Output disabled asynchronously in a low state Description Byte 3: Silicon Register (Read Only) Bit 7 6 5 4 3 2 1 0 @Pup 1 0 0 0 0 0 0 0 Revision ID Pin # Vendor ID 1000 Cypress Description Document #: 38-07369 Rev. *A Page 5 of 10 CY28343 Maximum Ratings[5] Maximum Input Voltage Relative to VSS: ............. VSS - 0.5V Maximum Input Voltage Relative to VSS: ............ VSS + 0.7V Storage Temperature: ................................ -65C to + 150C Operating Temperature: .................................... 0C to +70C Maximum ESD Protection:...........................................2000V Maximum Power Supply: ................................................5.5V This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). Condition SDATA, SCLK 2.2 CLKIN, FBIN_SDR CLKIN, FBIN_DDR CLKIN, FBIN_SDR CLKIN, FBIN_DDR VO = GND or VO = VDD FO = 133 MHz -0.3 -0.3 2.0 1.7 -10 235 4 0.8 0.7 VDD + 0.3 VDD + 0.3 10 300 DC Parameters[6]: TA = 0C to +70C Parameter VIL VIH VIL VIL VIH VIH IOZ IDDQ Cin Description Input Low Voltage Input High Voltage CLKIN Input Low Voltage (SDR Mode, VDD_3.3V = 3.3V) CLKIN Input Low Voltage (DDR Mode, VDD_2.5V = 2.5V) CLKIN Input High Voltage (SDR Mode, VDD_3.3V = 3.3V) CLKIN Input High Voltage (DDR Mode, VDD_2.5V = 2.5V) High-Impedance Output Current Dynamic Supply Current[7] Input Pin Capacitance Min. Typ. Max. 1.0 Unit V V V V V V mA ma pF Table 5. AC Parameters for DDRT/C (0:5): VDD_2.5V = 2.5V 5%, AVDD_3.3V = 3.3V 5%, TA = 0C to +70C Parameter fCLK tDCI tDCO tLOCK[9] Tr/Tf tpZL, tpZH tpLZ, tpHZ tHPJ tPHASE tSKEW VOUT Vx Description Operating Clock Frequency Input Clock Duty Cycle Output Clock Duty Cycle Maximum PLL Lock Time Output Clocks Slew Rate Output Enable Time[8](all [8](all Condition VDD_2.5V = 2.5V 5% Min. 99 45 47 Typ. Max. 170 55 Unit MHz % % ms V/ns ns ns ps ps ps V V 50 53 1.5 20% to 80% of VDD_2.5V outputs) outputs) @100 MHz and 133 MHz @133 MHz Skew[7] 1.0 3 3 90 2.3 5 5 125 200 150 Output Disable Time Half-Period Jitter Phase Error Any Output to Any Output Output Voltage Swing[7] 1.1 (VDD/2) - 0.2 VDD/2 VDD - 0.4 (VDD/2) + 0.2 Output Crossing Voltage[7] Notes: 5. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 6. Unused inputs must be held high or low to prevent them from floating. 7. All differential output terminals are terminated with 120/16 pF as shown in Figure 4. 8. Refers to the transition of non-inverting output. 9. Time required for the integrated PL circuit to obtain phase lock of its feed back signal to its reference signal. For Phase lock specifications for propagation delay, skew and jitter parameters given in the switching characteristics table are not applicable. Document #: 38-07369 Rev. *A Page 6 of 10 CY28343 Table 6. AC Parameters for SDRAM Outputs: VDD_3.3V = 2.5V 5%, AVDD_3.3V = 3.3V 5%, TA = 0C to +70C Parameter fCLK tDCI tLOCK[9] tDCO Tr/Tf 12] [10, 11, Description Operating Clock Frequency Input Clock Duty Cycle Maximum PLL Lock Time Output Clock Duty Cycle Output Clocks Slew Rate Output Enable Time (all outputs) Output Disable Time (all outputs) Cycle-to-Cycle Jitter Phase Error Any Output to Any Output Skew[11] Output Voltage Swing[11] [11] Condition VDD_3.3V = 3.3V 5% Min 99 45 Typ Max 133 55 1.5 Unit MHz % ms % ps ns ns ps ps ps V V 100 MHz, 133 MHz 45 0.4 50 55 1.6 tpZL, tpZH tpLZ, tpHZ tCCJ tPHASE tSKEW VOUT 3 3 @133 MHz @133 MHz 90 5 5 200 400 200 1.1 VDD - 0.4 0.2 (VDD/2) - 0.2 VDD/2 (VDD/2) + Vx Output Crossing Voltage Notes: 10. The tSKEW specification is only valid for equal loading of all outputs (30 pF lump-load). Measurement are acquired at 1.5V for 3.3V signals. 11. The test load is 30 pF lump-load. 12. TR/TF are measured at 0.4V to 2.4V. Differential Parameter Measurement Information 1.25V /1.5V 1.25V C K _IN 1.25V /1.5 V 1.2 5V F B IN t ( )n t ( )n = t ( )n +1 n1 N N = t ( )n ( N is large num ber o f sam ples) Figure 1. Phase Error Document #: 38-07369 Rev. *A Page 7 of 10 CY28343 DDRCX DDRTX DDRCX DDRTX ts k (o ) Figure 2. Output Skew DDRCx DDRTx tc (n ) t c (n + 1 ) t jit (c c ) = t c ( n )- t c (n + 1 ) Figure 3. Cycle-to-Cycle Jitter TPCB DDRT 2 pF Measurement Point 120 TPCB 2 pF DDRC Measurement Point Figure 4. Differential Signal Using Direct Terminal Resistor Document #: 38-07369 Rev. *A Page 8 of 10 CY28343 Ordering Information Part Number CY28343OC CY28343OCT Package Type 48-pin SSOP 48-pin SSOP - Tape and Reel Product Flow Commercial, 0 to 70C Commercial, 0 to 70C Package Drawing and Dimensions 48-Lead Shrunk Small Outline Package O48 51-85061-C All product and company names mentioned in this document may be the trademarks of their respective owners. Document #: 38-07369 Rev. *A Page 9 of 10 (c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY28343 Document Title:CY28343 Zero Delay SDR/DDR Clock Buffer Document #: 38-07369 Rev. ** *A ECN No. 116671 122909 Issue Date 08/22/02 12/26/02 Orig. of Change DMG RBI New Data Sheet Add power up requirements to maximum ratings information Description of Change Document #: 38-07369 Rev. *A Page 10 of 10 |
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